SOI wafers are superior to conventional silicon wafers in terms of inter-element separation, reduction of parasitic capacitance between elements and substrate, and three-dimensional structure, and are used in high-speed, low-power-consumption LSI. Lamination methods are used to produce SOI wafers. These methods consist of forming an oxide film and bonding two silicon wafers followed by grinding and polishing to form an SOI layer. In addition, the Smart Cut method (registered trademark) is included in these lamination methods.
In addition, SOI layers have recently come to be required to be thinner and have a more uniform thickness in the aforementioned SOI manufacturing methods. Although chemical mechanical polishing (CMP) is currently used to reduce thickness in the Smart Cut method, this requirement is unable to be met due to the difficulty of uniformly polishing the entire wafer surface with high precision. Technologies like that described in the following Patent Document 1, for example, have been proposed to reduce thickness and achieve uniform thickness of SOI layers. Namely, while an oxide film is formed on a base wafer, a highly concentrated impurity layer of boron and so forth is formed on an active layer wafer surface by thermal diffusion or ion implantation followed by lamination thereof. Next, the active layer wafer side is ground and the silicon portion remaining after grinding is etched to expose the highly concentrated impurity layer. Moreover, the highly concentrated impurity layer is oxidized and this oxide film is removed with HF solution to prepare an SOI wafer.
In addition, the following technology is proposed in the following Patent Document 2. Namely, in the preparation of SOI wafers by the Smart Cut method, the wafer surface is first subjected to oxidation treatment following separation to form an oxide film. The oxide film is then removed using an aqueous HF solution. Subsequently, the wafer is heat treated in a reducing atmosphere containing hydrogen to smooth the surface.
Normally, when reducing SOI thickness, the uniformity of the in-plane film thickness is required to be 5 to 10% or less. If this is not satisfied, there is a considerable effect on the electrical characteristics (for example, variations in switching time) of the transistor formed on the SOI layer.
However, according to the technology described in the aforementioned Patent Document 1, in the case of etching silicon remaining on the ground surface, there are no large differences between the etching rate for the Si of the etching liquid and that for the highly concentrated impurity layer. Thus, when the Si surface is etched after grinding, the highly concentrated impurity layer is also etched, and uniform in-plane thickness of the highly concentrated impurity layer is not obtained. Accordingly, in-plane uniformity cannot be retained for the film thickness of the SOI layer.
In addition, according to the technology described in the Patent Document 2, smoothing treatment is carried out by utilizing the etching effects of hydrogen gas. However, since a vertical oven is used during this hydrogen annealing or argon gas annealing, it is difficult to control the etching rates according to the gas between the center and outer edge of the SOI wafer due to the non-uniformity of gas flow. Consequently, etching unevenness occurs easily and the film thickness of the SOI layer becomes non-uniform due to this etching unevenness.
[Patent Document 1]Japanese Unexamined Patent Application, FirstPublication, (JP-A) No. H09-116125[Patent Document 2]Japanese Unexamined Patent Application, FirstPublication, (JP-A) No. 2000-124092